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sp added.
[motonesfpga/motonesfpga.git] / de0_cv_nes / simulation /
2016-09-17 astoria-dsp added.
2016-09-17 astoria-dinst decode until a2 created.
2016-09-16 astoria-d@fcupdate work...
2016-09-16 astoria-d@fcupdate
2016-09-16 astoria-d@fcio bus, r/w, inst reg set ok.
2016-09-15 astoria-d@fcmain/sub state transition added. currently fake inst...
2016-09-14 astoria-d@fcsprite pattern shift ok.
2016-09-13 astoria-d@fcsprite pattern fetch ok
2016-09-13 astoria-d@fcsprite copy ok.
2016-09-12 astoria-d@fcspr evaluation ok.
2016-09-12 astoria-d@fcoam clear ok
2016-09-12 astoria-d@fcsprite state machine added
2016-09-11 astoria-dshift register timing changed.
2016-09-11 astoria-dwrong pattern shift timing.
2016-09-11 astoria-ddummy testbench updated to emulate ram/rom access.
2016-09-11 astoria-dbg display not work. dbg counter added.
2016-09-10 astoria-dvga work.
2016-09-10 astoria-dstii debug start. vga display failed!!
2016-09-10 astoria-dbg display done with rtl...
2016-09-10 astoria-dpalette bus separated.
2016-09-10 astoria-dbg pattern ok on rtl.
2016-09-10 astoria-drender working...
2016-09-10 astoria-dvram access cs set ok.
2016-09-10 astoria-dpos work...
2016-09-10 astoria-drender x, y reg set.
2016-09-10 astoria-dvga rendering start.
2016-09-10 astoria-dsprite ram added.
2016-09-10 astoria-dvram set integration ok.
2016-09-10 astoria-dvram instance integrated.
2016-09-09 astoria-dppu register set working...
2016-09-09 astoria-d@fcdummy cpu stub ok.
2016-09-08 astoria-d@fcclock enabler update
2016-09-08 astoria-d@fcrtl sim started...
2016-09-08 astoria-d@fcclean up
2016-09-08 astoria-d@fcclea up
2016-07-17 astoria-dMerge branch 'ppu_test'
2016-05-20 astoria-d@officesignal trap ii set up
2016-05-19 astoria-d@officesimulation env setup ok