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pof generate memo added.
[motonesfpga/motonesfpga.git] / de1_nes /
2016-10-05 astoria-dupdate
2016-09-19 astoria-dall regression test ok, display all ok! ppu-work-160919
2016-09-05 astoria-dmore work. all codes must be written in synchronized... ppu-work-160905
2016-09-05 astoria-dupdate
2016-09-04 astoria-dppu reg read added
2016-09-04 astoria-dppu read test patern added
2016-09-03 astoria-dbg, sprite all ok on de1 board!! ppu-work-160903
2016-09-03 astoria-dspr attr reg added.
2016-09-03 astoria-dsprite bug fix
2016-09-03 astoria-dsprite reg update enabler timing changed..
2016-09-03 astoria-dsprite display more work..
2016-09-03 astoria-dmore spr test
2016-09-03 astoria-dsprite work more
2016-09-03 astoria-dsprite working..
2016-09-03 astoria-ddebug sprite on gate leve
2016-09-02 astoria-drtl sim ok for sprite. testbench update
2016-09-02 astoria-ddiferred reg timing changed.
2016-09-02 astoria-dpalette color and data register added. color more vivd...
2016-08-28 astoria-dbg scrolling ok.
2016-08-28 astoria-denabled scroll test ok...
2016-08-28 astoria-dvram timing changed.
2016-08-28 astoria-dvram timing changed (restored).
2016-08-28 astoria-dppu deferred clock added, ram timing changed.
2016-08-28 astoria-dadded vram access register. currently bg displayed...
2016-08-27 astoria-dscrolling ok, but now scroll happens only 8 pix each...
2016-08-27 astoria-dbg edge display bug fixed. scrolling sitll not correct.
2016-08-27 astoria-dde0-cv sync.
2016-08-27 astoria-dbg test ok, except for scrolling. sprite not displayed.
2016-08-27 astoria-dppu work update ppu-work-160827
2016-08-27 astoria-dvram mem clock deferred.
2016-08-27 astoria-dale direction opposite...
2016-08-27 astoria-dale simplified.
2016-08-27 astoria-dvaddr decoder bug fix.
2016-08-27 astoria-dvram addressing method changed.
2016-08-27 astoria-dvram access (attr tbl) timing complied to the nes speci...
2016-08-27 astoria-dvram addr set timing changed
2016-08-27 astoria-dscript update
2016-08-27 astoria-dlatch clean up
2016-08-27 astoria-dvram latch addr output timing changed
2016-08-27 astoria-dbg enabled.
2016-08-27 astoria-dgate sim ok. still working
2016-08-27 astoria-dtestbench update
2016-08-27 astoria-dvram access changed
2016-08-27 astoria-dsprite enabled, still working...
2016-08-27 astoria-dplt ram access added
2016-08-18 astoria-d@fcmore render integration..
2016-08-18 astoria-d@fcvga render inst integrated.
2016-08-18 astoria-d@fcppu reg code clean up
2016-08-16 astoria-d@fcvram latch bug fixed...
2016-08-16 astoria-d@fcstill working... vram addr is incorrect.
2016-08-16 astoria-d@fccpu clock timing changed. 1/16 of base clock (accelarated).
2016-08-16 astoria-d@fcvram work...
2016-08-16 astoria-d@fcppu working...
2016-08-16 astoria-d@fccount up reg impl updated.
2016-08-15 astoria-dvram timing debugging...
2016-08-15 astoria-d@fcvram access degraded... must investigate.
2016-08-15 astoria-d@fcupdate
2016-08-15 astoria-d@fcale bug fix..
2016-08-15 astoria-d@fcvram latch update
2016-08-15 astoria-d@fcvram access added.
2016-08-14 astoria-dgate level sim ok.
2016-08-14 astoria-dppu reg set ok..
2016-08-14 astoria-dppu register set func re-writing...
2016-08-14 astoria-dtest env update
2016-08-14 astoria-dtest env update...
2016-08-14 astoria-dcpu prom restored for gate level tests..
2016-08-14 astoria-dppu test evn update.
2016-08-14 astoria-dppu work env update
2016-08-14 astoria-dstart ppu re-working.. test update.
2016-08-14 astoria-dbranch page crossing bug fixed.
2016-08-13 astoria-dgate level simulation ok cpu-work-160813
2016-08-13 astoria-dindir y bus update timing fix.
2016-08-13 astoria-dstatus reg update timing bug fixed.
2016-08-13 astoria-dalu bug fix.
2016-08-13 astoria-dram/rom garbage data eliminated.
2016-08-13 astoria-djsr cycle complied to the h/w manual.
2016-08-13 astoria-dpc and sp clock timing changed (again restored!)
2016-08-13 astoria-dpcl inc bug fix.
2016-08-12 astoria-d@fcdecoder set clock added (you can say this is rollback!).
2016-08-12 astoria-d@fcanother phase delayed clock added.
2016-08-12 astoria-d@fcaddr calc bug fix.
2016-08-12 astoria-d@fcupdate modelsim tcl script.
2016-08-11 astoria-d@fcminor change
2016-08-11 astoria-d@fcupdate
2016-08-11 astoria-d@fcreset vector ok
2016-08-11 astoria-d@fcadded delayed mem clock.
2016-08-11 astoria-d@fcupdate
2016-08-11 astoria-d@fcnew clock timing design... rtl test env setup ok.
2016-08-11 astoria-d@fcppu test module bug fix.
2016-08-08 astoria-dexec cycle rework. still a lot to go!
2016-08-08 astoria-dcpu rework... damn!!!
2016-08-08 astoria-dmore ppu work...
2016-08-08 astoria-dppu ram timing working...
2016-08-08 astoria-dppu rework...
2016-08-08 astoria-ddisplay degration solved.... ppu-work-160808
2016-08-07 astoria-dppu ram timing changed, but not working yet...
2016-08-06 astoria-dtiming adjustment...
2016-08-06 astoria-dclock driver changed
2016-08-06 astoria-dmerge ppu_test
2016-08-06 astoria-dsdc added. must rework for timing again... all clocks...
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