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motonesfpga/motonesfpga.git
2016-09-10
astoria-d
palette bus separated.
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2016-09-10
astoria-d
bg pattern ok on rtl.
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2016-09-10
astoria-d
render working...
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2016-09-10
astoria-d
vram access cs set ok.
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2016-09-10
astoria-d
pos work...
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2016-09-10
astoria-d
render x, y reg set.
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2016-09-10
astoria-d
vga rendering start.
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2016-09-10
astoria-d
sprite ram added.
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2016-09-10
astoria-d
ppu source dir created
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2016-09-10
astoria-d
vram set integration ok.
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2016-09-10
astoria-d
vram instance integrated.
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2016-09-09
astoria-d
ppu register set working...
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2016-09-09
astoria-d@fc
ppu integration start...
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2016-09-09
astoria-d@fc
addr decoder added
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2016-09-09
astoria-d@fc
dummy cpu stub ok.
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2016-09-08
astoria-d@fc
update
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2016-09-08
astoria-d@fc
clock enabler update
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2016-09-08
astoria-d@fc
rtl sim started...
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2016-09-08
astoria-d@fc
new design work...
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2016-09-08
astoria-d@fc
new design work started.
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2016-09-08
astoria-d@fc
clean up
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2016-09-08
astoria-d@fc
clea up
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2016-09-08
astoria-d@fc
renewed de0-cv all files!
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2016-09-08
astoria-d@fc
new block design added
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2016-09-08
astoria-d@fc
exec cycle doc update
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2016-09-07
astoria-d@fc
new state machine design added
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2016-09-05
astoria-d
more work. all codes must be written in synchronized...
ppu-work-160905
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2016-09-05
astoria-d
de1 integration. failed to display..
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2016-09-05
astoria-d
update
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2016-09-04
astoria-d
ppu reg read added
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2016-09-04
astoria-d
ppu read test patern added
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2016-09-04
astoria-d
de0-cv integration ok.
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2016-09-04
astoria-d
added de0-cv manual
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2016-09-04
astoria-d
dma test update ok
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2016-09-03
astoria-d
bg, sprite all ok on de1 board!!
ppu-work-160903
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2016-09-03
astoria-d
spr attr reg added.
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2016-09-03
astoria-d
sprite bug fix
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2016-09-03
astoria-d
sprite reg update enabler timing changed..
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2016-09-03
astoria-d
sprite display more work..
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2016-09-03
astoria-d
more spr test
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2016-09-03
astoria-d
doc update
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2016-09-03
astoria-d
sprite work more
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2016-09-03
astoria-d
sprite working..
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2016-09-03
astoria-d
debug sprite on gate leve
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2016-09-02
astoria-d
rtl sim ok for sprite. testbench update
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2016-09-02
astoria-d
diferred reg timing changed.
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2016-09-02
astoria-d
palette color and data register added. color more vivd...
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2016-08-28
astoria-d
bg scrolling ok.
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2016-08-28
astoria-d
enabled scroll test ok...
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2016-08-28
astoria-d
vram timing changed.
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2016-08-28
astoria-d
vram timing changed (restored).
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2016-08-28
astoria-d
ppu deferred clock added, ram timing changed.
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2016-08-28
astoria-d
added vram access register. currently bg displayed...
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2016-08-28
astoria-d
scroll doc update
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2016-08-28
astoria-d
fuck de0-cv. doesn't work at all!!!!
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2016-08-28
astoria-d
st ii clock counter enabled. bg not displayed again..
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2016-08-28
astoria-d
de0-cv integration ok, bg displayed on the test image.
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2016-08-27
astoria-d
scrolling ok, but now scroll happens only 8 pix each...
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2016-08-27
astoria-d
bg edge display bug fixed. scrolling sitll not correct.
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2016-08-27
astoria-d
de0-cv sync.
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2016-08-27
astoria-d
de0-cv bg display ok. debug counter was disabled...
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2016-08-27
astoria-d
de0-cv latest merge
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2016-08-27
astoria-d
testbench eliminated from de0-cv
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2016-08-27
astoria-d
bg test ok, except for scrolling. sprite not displayed.
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2016-08-27
astoria-d
ppu work update
ppu-work-160827
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2016-08-27
astoria-d
vram mem clock deferred.
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2016-08-27
astoria-d
ale direction opposite...
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2016-08-27
astoria-d
ale simplified.
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2016-08-27
astoria-d
vaddr decoder bug fix.
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2016-08-27
astoria-d
vram addressing method changed.
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2016-08-27
astoria-d
vram access (attr tbl) timing complied to the nes speci...
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2016-08-27
astoria-d
vram addr set timing changed
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2016-08-27
astoria-d
script update
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2016-08-27
astoria-d
latch clean up
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2016-08-27
astoria-d
vram latch addr output timing changed
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2016-08-27
astoria-d
bg enabled.
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2016-08-27
astoria-d
gate sim ok. still working
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2016-08-27
astoria-d
testbench update
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2016-08-27
astoria-d
vram access changed
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2016-08-27
astoria-d
sprite enabled, still working...
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2016-08-27
astoria-d
plt ram access added
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2016-08-18
astoria-d@fc
more render integration..
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2016-08-18
astoria-d@fc
vga render inst integrated.
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2016-08-18
astoria-d@fc
ppu reg code clean up
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2016-08-16
astoria-d@fc
vram latch bug fixed...
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2016-08-16
astoria-d@fc
still working... vram addr is incorrect.
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2016-08-16
astoria-d@fc
cpu clock timing changed. 1/16 of base clock (accelarated).
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2016-08-16
astoria-d@fc
vram work...
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2016-08-16
astoria-d@fc
ppu working...
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2016-08-16
astoria-d@fc
count up reg impl updated.
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2016-08-15
astoria-d
vram timing debugging...
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2016-08-15
astoria-d@fc
vram access degraded... must investigate.
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2016-08-15
astoria-d@fc
update
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2016-08-15
astoria-d@fc
ale bug fix..
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2016-08-15
astoria-d@fc
vram latch update
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2016-08-15
astoria-d@fc
vram access added.
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2016-08-14
astoria-d
gate level sim ok.
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2016-08-14
astoria-d
ppu reg set ok..
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2016-08-14
astoria-d
ppu register set func re-writing...
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2016-08-14
astoria-d
test env update
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