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astoria-d@office [Thu, 15 Jan 2015 05:13:43 +0000 (14:13 +0900)]
BG image displayed on the real VGA monitor!!!
unknown [Wed, 14 Jan 2015 10:51:09 +0000 (19:51 +0900)]
vga edge reset adjustment
unknown [Wed, 14 Jan 2015 09:36:05 +0000 (18:36 +0900)]
address latch integration ok
astoria-d [Mon, 12 Jan 2015 14:11:40 +0000 (23:11 +0900)]
vram r/w working
astoria-d [Mon, 12 Jan 2015 02:53:49 +0000 (11:53 +0900)]
rtl simulation env set up.
astoria-d [Sun, 11 Jan 2015 10:43:11 +0000 (19:43 +0900)]
more debug... vga is displayed but still image is broken
astoria-d [Fri, 9 Jan 2015 11:44:34 +0000 (20:44 +0900)]
ppu vga working
astoria-d [Fri, 9 Jan 2015 07:45:25 +0000 (16:45 +0900)]
added vram init sequence
astoria-d [Fri, 9 Jan 2015 03:22:40 +0000 (12:22 +0900)]
debug env update, chr rom added
astoria-d [Fri, 9 Jan 2015 02:38:36 +0000 (11:38 +0900)]
vram components added.
astoria-d [Fri, 9 Jan 2015 01:40:57 +0000 (10:40 +0900)]
debug pins added
astoria-d [Fri, 9 Jan 2015 00:46:33 +0000 (09:46 +0900)]
integration working
astoria-d [Fri, 9 Jan 2015 00:44:22 +0000 (09:44 +0900)]
start ppu impl integration
astoria-d [Tue, 6 Jan 2015 11:15:22 +0000 (20:15 +0900)]
minor update
astoria-d [Tue, 6 Jan 2015 11:07:06 +0000 (20:07 +0900)]
Merge branch 'ppu_test' of git.sourceforge.jp:/gitroot/motonesfpga/motonesfpga into ppu_test
astoria-d [Tue, 6 Jan 2015 11:04:49 +0000 (20:04 +0900)]
emulated ppu clock added
unknown [Tue, 6 Jan 2015 09:44:59 +0000 (18:44 +0900)]
doc update
astoria-d [Tue, 6 Jan 2015 09:28:31 +0000 (18:28 +0900)]
prepared vga rendering template
astoria-d [Tue, 6 Jan 2015 04:50:29 +0000 (13:50 +0900)]
vga render integration
astoria-d [Tue, 6 Jan 2015 02:30:41 +0000 (11:30 +0900)]
old render module integrated. now we can start working...
astoria-d [Tue, 6 Jan 2015 01:55:10 +0000 (10:55 +0900)]
new ppm test env set up
astoria-d [Tue, 6 Jan 2015 01:09:59 +0000 (10:09 +0900)]
new ppu/vga integration set up
astoria-d [Tue, 6 Jan 2015 00:17:50 +0000 (09:17 +0900)]
env adjustment
unknown [Mon, 5 Jan 2015 10:02:02 +0000 (19:02 +0900)]
sdram controller eliminated
unknown [Mon, 5 Jan 2015 09:45:55 +0000 (18:45 +0900)]
simulation env updated
unknown [Mon, 5 Jan 2015 09:20:21 +0000 (18:20 +0900)]
merge files from master
unknown [Mon, 5 Jan 2015 09:19:30 +0000 (18:19 +0900)]
merge master files
astoria-d [Mon, 16 Dec 2013 05:00:57 +0000 (14:00 +0900)]
update
astoria-d [Tue, 3 Dec 2013 08:32:19 +0000 (17:32 +0900)]
test clean up
astoria-d [Tue, 3 Dec 2013 07:52:28 +0000 (16:52 +0900)]
ppu test env set up ok...
astoria-d [Tue, 3 Dec 2013 06:18:34 +0000 (15:18 +0900)]
ppu test env setup
astoria-d [Tue, 3 Dec 2013 06:17:26 +0000 (15:17 +0900)]
update
astoria-d [Thu, 28 Nov 2013 06:19:52 +0000 (15:19 +0900)]
simulation minimum interval changed due to pll simulation
astoria-d [Thu, 28 Nov 2013 05:56:33 +0000 (14:56 +0900)]
- merged latest render module
- render pos timing updated
astoria-d [Fri, 22 Nov 2013 04:33:47 +0000 (13:33 +0900)]
sdram & vga integrated, not displayed though....
astoria-d [Fri, 22 Nov 2013 04:26:47 +0000 (13:26 +0900)]
pll lock signal added
pll frequency changed to 166.666
astoria-d [Fri, 22 Nov 2013 03:29:05 +0000 (12:29 +0900)]
sdram clk singal change
astoria-d [Sat, 9 Nov 2013 23:28:17 +0000 (08:28 +0900)]
page crossing branch instruction supported!!
astoria-d [Sat, 9 Nov 2013 07:41:46 +0000 (16:41 +0900)]
mem clock updated to 160 MHz
astoria-d [Sun, 3 Nov 2013 06:02:35 +0000 (15:02 +0900)]
vga working
astoria-d [Sun, 27 Oct 2013 03:13:18 +0000 (12:13 +0900)]
test image added
astoria-d [Sun, 27 Oct 2013 03:05:08 +0000 (12:05 +0900)]
ppu address reg set timing updated
astoria-d [Sun, 20 Oct 2013 01:41:43 +0000 (10:41 +0900)]
clean up
astoria-d [Sun, 20 Oct 2013 01:37:14 +0000 (10:37 +0900)]
clean up
astoria-d [Sun, 20 Oct 2013 01:21:28 +0000 (10:21 +0900)]
sdram control clean up
astoria-d [Sat, 19 Oct 2013 11:54:59 +0000 (20:54 +0900)]
sdram integration ok
astoria-d [Sat, 19 Oct 2013 04:53:34 +0000 (13:53 +0900)]
sdram controller integration
astoria-d [Mon, 14 Oct 2013 01:31:36 +0000 (10:31 +0900)]
vga work...
astoria-d [Sat, 12 Oct 2013 10:04:35 +0000 (19:04 +0900)]
vga output working...
astoria-d [Sat, 12 Oct 2013 00:49:08 +0000 (09:49 +0900)]
test vga output working...
astoria-d [Sat, 12 Oct 2013 00:32:17 +0000 (09:32 +0900)]
Merge branch 'master' of git.sourceforge.jp:/gitroot/motonesfpga/motonesfpga
astoria-d [Sat, 12 Oct 2013 00:31:57 +0000 (09:31 +0900)]
vga output ok!!
astoria-d [Tue, 8 Oct 2013 02:32:12 +0000 (11:32 +0900)]
test update
astoria-d [Tue, 8 Oct 2013 02:22:25 +0000 (11:22 +0900)]
jmp (ind) test added.
astoria-d [Tue, 8 Oct 2013 02:10:33 +0000 (11:10 +0900)]
a5 instruction test added.
astoria-d [Mon, 7 Oct 2013 08:27:46 +0000 (17:27 +0900)]
a4 instructions regression test added.
astoria-d [Mon, 7 Oct 2013 06:56:25 +0000 (15:56 +0900)]
a2, a3 instruction test added.
astoria-d [Mon, 7 Oct 2013 03:10:08 +0000 (12:10 +0900)]
tsx instruction supported.
astoria-d [Sun, 6 Oct 2013 04:49:41 +0000 (13:49 +0900)]
vga woring...
astoria-d [Sat, 5 Oct 2013 08:26:36 +0000 (17:26 +0900)]
vga test proj added. still working...
astoria-d [Sat, 5 Oct 2013 01:24:05 +0000 (10:24 +0900)]
ppu render debug pin added but cyclone ii runs short of output pin!
astoria-d [Sat, 5 Oct 2013 01:02:49 +0000 (10:02 +0900)]
oam data read was ok???
previsous changed didn't need. restored.
astoria-d [Sat, 5 Oct 2013 00:36:55 +0000 (09:36 +0900)]
ppu integration and bug fix
astoria-d [Fri, 4 Oct 2013 08:47:42 +0000 (17:47 +0900)]
regression test single byte inst test ok
astoria-d [Fri, 4 Oct 2013 07:32:36 +0000 (16:32 +0900)]
- ppu render ram write timing updated.
- code clean up
astoria-d [Fri, 4 Oct 2013 06:39:30 +0000 (15:39 +0900)]
regression test update
astoria-d [Fri, 4 Oct 2013 05:48:04 +0000 (14:48 +0900)]
regression test update
astoria-d [Fri, 4 Oct 2013 03:30:12 +0000 (12:30 +0900)]
regression test updated.
astoria-d [Wed, 2 Oct 2013 03:09:44 +0000 (12:09 +0900)]
regression test update
astoria-d [Tue, 1 Oct 2013 09:05:27 +0000 (18:05 +0900)]
regression test updated (print func ok.)
astoria-d [Tue, 1 Oct 2013 08:48:02 +0000 (17:48 +0900)]
regression test working...
astoria-d [Tue, 1 Oct 2013 01:40:44 +0000 (10:40 +0900)]
regression test created
astoria-d [Mon, 30 Sep 2013 09:55:20 +0000 (18:55 +0900)]
ppu integrated. still working...
astoria-d [Mon, 30 Sep 2013 07:10:24 +0000 (16:10 +0900)]
- input data latch invalid data latch bug fixed.
- debug pins added.
astoria-d [Mon, 30 Sep 2013 06:23:40 +0000 (15:23 +0900)]
modified input data latch to stop using latch, but use dff.
astoria-d [Mon, 30 Sep 2013 06:17:15 +0000 (15:17 +0900)]
segment size fixed
astoria-d [Mon, 30 Sep 2013 05:25:25 +0000 (14:25 +0900)]
Merge branch 'master' of git.sourceforge.jp:/gitroot/motonesfpga/motonesfpga
astoria-d [Mon, 30 Sep 2013 05:24:31 +0000 (14:24 +0900)]
de1 env test case added.
astoria-d [Mon, 30 Sep 2013 04:44:11 +0000 (13:44 +0900)]
segment size modified
astoria-d [Mon, 30 Sep 2013 04:11:03 +0000 (13:11 +0900)]
merge updates
astoria-d [Mon, 30 Sep 2013 01:40:01 +0000 (10:40 +0900)]
- name tbl 0/1 write clock synchronized
astoria-d [Mon, 30 Sep 2013 01:21:10 +0000 (10:21 +0900)]
added .gitignore file
astoria-d [Sun, 29 Sep 2013 10:14:40 +0000 (19:14 +0900)]
async param test
astoria-d [Fri, 27 Sep 2013 01:53:40 +0000 (10:53 +0900)]
ram timing ctrl modified.
astoria-d [Fri, 27 Sep 2013 01:37:00 +0000 (10:37 +0900)]
- merge decoder updates
- testbench update
astoria-d [Thu, 26 Sep 2013 07:29:26 +0000 (16:29 +0900)]
test timing aligned.
astoria-d [Thu, 26 Sep 2013 06:45:49 +0000 (15:45 +0900)]
- decoder clean up
- clock synchronized ram integrated
- abs addr mode bug working...
astoria-d [Thu, 26 Sep 2013 05:46:53 +0000 (14:46 +0900)]
merge updates
astoria-d [Thu, 26 Sep 2013 02:27:53 +0000 (11:27 +0900)]
ram write timing changed
astoria-d [Thu, 26 Sep 2013 02:16:53 +0000 (11:16 +0900)]
- module structure reorganizezd
- chrrom to be clock synchronized
- ram to be clock synchronized (still working...)
astoria-d [Wed, 25 Sep 2013 10:21:42 +0000 (19:21 +0900)]
clean up
astoria-d [Wed, 25 Sep 2013 10:20:10 +0000 (19:20 +0900)]
status register bug fixed!!
astoria-d [Wed, 25 Sep 2013 09:34:23 +0000 (18:34 +0900)]
status reg test ok
astoria-d [Wed, 25 Sep 2013 05:31:13 +0000 (14:31 +0900)]
- ghdl env merge
- dual dff debug port added
- status debug working
astoria-d [Wed, 25 Sep 2013 04:32:27 +0000 (13:32 +0900)]
code merge
astoria-d [Wed, 25 Sep 2013 01:55:10 +0000 (10:55 +0900)]
wrong segment number fixed
astoria-d [Wed, 25 Sep 2013 01:50:42 +0000 (10:50 +0900)]
4k segment remapping added to test app.
astoria-d [Wed, 25 Sep 2013 01:27:57 +0000 (10:27 +0900)]
clean up
astoria-d [Wed, 25 Sep 2013 01:24:55 +0000 (10:24 +0900)]
code clean up
astoria-d [Wed, 25 Sep 2013 01:02:20 +0000 (10:02 +0900)]
module structure re-organized
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