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astoria-d [Sun, 11 Sep 2016 08:15:32 +0000 (17:15 +0900)]
bg display ok!!!
astoria-d [Sun, 11 Sep 2016 08:02:08 +0000 (17:02 +0900)]
shift register timing changed.
astoria-d [Sun, 11 Sep 2016 06:16:36 +0000 (15:16 +0900)]
wrong pattern shift timing.
astoria-d [Sun, 11 Sep 2016 05:45:45 +0000 (14:45 +0900)]
pattern test
astoria-d [Sun, 11 Sep 2016 03:57:51 +0000 (12:57 +0900)]
st ii work. signal captured.
astoria-d [Sun, 11 Sep 2016 03:46:24 +0000 (12:46 +0900)]
update
astoria-d [Sun, 11 Sep 2016 03:07:57 +0000 (12:07 +0900)]
vram timing update.
astoria-d [Sun, 11 Sep 2016 02:41:25 +0000 (11:41 +0900)]
dummy testbench updated to emulate ram/rom access.
astoria-d [Sun, 11 Sep 2016 01:27:57 +0000 (10:27 +0900)]
bg display not work. dbg counter added.
astoria-d [Sat, 10 Sep 2016 16:57:07 +0000 (01:57 +0900)]
vga work.
astoria-d [Sat, 10 Sep 2016 16:52:13 +0000 (01:52 +0900)]
vga ok.
astoria-d [Sat, 10 Sep 2016 16:30:39 +0000 (01:30 +0900)]
stii debug start. vga display failed!!
astoria-d [Sat, 10 Sep 2016 15:10:05 +0000 (00:10 +0900)]
wront param name fixed.
astoria-d [Sat, 10 Sep 2016 15:06:18 +0000 (00:06 +0900)]
dma testbench setup timing violation. why??
astoria-d [Sat, 10 Sep 2016 14:51:56 +0000 (23:51 +0900)]
bg display done with rtl...
astoria-d [Sat, 10 Sep 2016 14:26:10 +0000 (23:26 +0900)]
palette bus separated.
astoria-d [Sat, 10 Sep 2016 13:24:44 +0000 (22:24 +0900)]
bg pattern ok on rtl.
astoria-d [Sat, 10 Sep 2016 12:04:39 +0000 (21:04 +0900)]
render working...
astoria-d [Sat, 10 Sep 2016 10:24:45 +0000 (19:24 +0900)]
vram access cs set ok.
astoria-d [Sat, 10 Sep 2016 04:41:00 +0000 (13:41 +0900)]
pos work...
astoria-d [Sat, 10 Sep 2016 04:35:00 +0000 (13:35 +0900)]
render x, y reg set.
astoria-d [Sat, 10 Sep 2016 03:53:01 +0000 (12:53 +0900)]
vga rendering start.
astoria-d [Sat, 10 Sep 2016 03:31:32 +0000 (12:31 +0900)]
sprite ram added.
astoria-d [Sat, 10 Sep 2016 02:36:31 +0000 (11:36 +0900)]
ppu source dir created
astoria-d [Sat, 10 Sep 2016 02:33:35 +0000 (11:33 +0900)]
vram set integration ok.
astoria-d [Sat, 10 Sep 2016 00:56:54 +0000 (09:56 +0900)]
vram instance integrated.
astoria-d [Fri, 9 Sep 2016 14:48:10 +0000 (23:48 +0900)]
ppu register set working...
astoria-d@fc [Fri, 9 Sep 2016 09:45:47 +0000 (18:45 +0900)]
ppu integration start...
astoria-d@fc [Fri, 9 Sep 2016 06:50:45 +0000 (15:50 +0900)]
addr decoder added
astoria-d@fc [Fri, 9 Sep 2016 06:23:15 +0000 (15:23 +0900)]
dummy cpu stub ok.
astoria-d@fc [Thu, 8 Sep 2016 12:43:33 +0000 (21:43 +0900)]
update
astoria-d@fc [Thu, 8 Sep 2016 12:42:15 +0000 (21:42 +0900)]
clock enabler update
astoria-d@fc [Thu, 8 Sep 2016 12:24:32 +0000 (21:24 +0900)]
rtl sim started...
astoria-d@fc [Thu, 8 Sep 2016 11:21:48 +0000 (20:21 +0900)]
new design work...
astoria-d@fc [Thu, 8 Sep 2016 11:05:29 +0000 (20:05 +0900)]
new design work started.
astoria-d@fc [Thu, 8 Sep 2016 10:55:11 +0000 (19:55 +0900)]
clean up
astoria-d@fc [Thu, 8 Sep 2016 10:53:28 +0000 (19:53 +0900)]
clea up
astoria-d@fc [Thu, 8 Sep 2016 10:52:46 +0000 (19:52 +0900)]
renewed de0-cv all files!
astoria-d@fc [Thu, 8 Sep 2016 10:47:17 +0000 (19:47 +0900)]
new block design added
astoria-d@fc [Thu, 8 Sep 2016 09:49:51 +0000 (18:49 +0900)]
exec cycle doc update
astoria-d@fc [Wed, 7 Sep 2016 13:01:22 +0000 (22:01 +0900)]
new state machine design added
astoria-d [Mon, 5 Sep 2016 13:16:45 +0000 (22:16 +0900)]
more work. all codes must be written in synchronized circuit!! thanks 2ch mate!
astoria-d [Mon, 5 Sep 2016 12:39:28 +0000 (21:39 +0900)]
de1 integration. failed to display..
astoria-d [Mon, 5 Sep 2016 12:00:22 +0000 (21:00 +0900)]
update
astoria-d [Sun, 4 Sep 2016 11:57:15 +0000 (20:57 +0900)]
ppu reg read added
astoria-d [Sun, 4 Sep 2016 05:51:37 +0000 (14:51 +0900)]
ppu read test patern added
astoria-d [Sun, 4 Sep 2016 05:13:25 +0000 (14:13 +0900)]
de0-cv integration ok.
astoria-d [Sun, 4 Sep 2016 05:12:49 +0000 (14:12 +0900)]
added de0-cv manual
astoria-d [Sun, 4 Sep 2016 04:43:53 +0000 (13:43 +0900)]
dma test update ok
astoria-d [Sat, 3 Sep 2016 12:26:01 +0000 (21:26 +0900)]
bg, sprite all ok on de1 board!!
astoria-d [Sat, 3 Sep 2016 12:25:21 +0000 (21:25 +0900)]
spr attr reg added.
astoria-d [Sat, 3 Sep 2016 11:27:40 +0000 (20:27 +0900)]
sprite bug fix
astoria-d [Sat, 3 Sep 2016 09:58:20 +0000 (18:58 +0900)]
sprite reg update enabler timing changed..
astoria-d [Sat, 3 Sep 2016 05:47:15 +0000 (14:47 +0900)]
sprite display more work..
astoria-d [Sat, 3 Sep 2016 05:24:57 +0000 (14:24 +0900)]
more spr test
astoria-d [Sat, 3 Sep 2016 03:28:14 +0000 (12:28 +0900)]
doc update
astoria-d [Sat, 3 Sep 2016 03:22:42 +0000 (12:22 +0900)]
sprite work more
astoria-d [Sat, 3 Sep 2016 02:48:17 +0000 (11:48 +0900)]
sprite working..
astoria-d [Sat, 3 Sep 2016 02:16:15 +0000 (11:16 +0900)]
debug sprite on gate leve
astoria-d [Fri, 2 Sep 2016 15:14:53 +0000 (00:14 +0900)]
rtl sim ok for sprite. testbench update
astoria-d [Fri, 2 Sep 2016 12:53:59 +0000 (21:53 +0900)]
diferred reg timing changed.
astoria-d [Fri, 2 Sep 2016 12:38:56 +0000 (21:38 +0900)]
palette color and data register added. color more vivd, stronger contrast. looks good.
bg color is wrong though, lol
astoria-d [Sun, 28 Aug 2016 13:25:55 +0000 (22:25 +0900)]
bg scrolling ok.
astoria-d [Sun, 28 Aug 2016 13:23:00 +0000 (22:23 +0900)]
enabled scroll test ok...
astoria-d [Sun, 28 Aug 2016 13:06:41 +0000 (22:06 +0900)]
vram timing changed.
astoria-d [Sun, 28 Aug 2016 13:04:55 +0000 (22:04 +0900)]
vram timing changed (restored).
astoria-d [Sun, 28 Aug 2016 13:04:16 +0000 (22:04 +0900)]
ppu deferred clock added, ram timing changed.
astoria-d [Sun, 28 Aug 2016 11:15:10 +0000 (20:15 +0900)]
added vram access register. currently bg displayed is broken.
astoria-d [Sun, 28 Aug 2016 10:36:44 +0000 (19:36 +0900)]
scroll doc update
astoria-d [Sun, 28 Aug 2016 09:40:06 +0000 (18:40 +0900)]
fuck de0-cv. doesn't work at all!!!!
astoria-d [Sun, 28 Aug 2016 08:00:15 +0000 (17:00 +0900)]
st ii clock counter enabled. bg not displayed again..
astoria-d [Sun, 28 Aug 2016 07:31:51 +0000 (16:31 +0900)]
de0-cv integration ok, bg displayed on the test image.
astoria-d [Sat, 27 Aug 2016 17:57:38 +0000 (02:57 +0900)]
scrolling ok, but now scroll happens only 8 pix each... strange!
astoria-d [Sat, 27 Aug 2016 15:28:30 +0000 (00:28 +0900)]
bg edge display bug fixed. scrolling sitll not correct.
astoria-d [Sat, 27 Aug 2016 14:33:44 +0000 (23:33 +0900)]
de0-cv sync.
astoria-d [Sat, 27 Aug 2016 14:30:14 +0000 (23:30 +0900)]
de0-cv bg display ok. debug counter was disabled...
astoria-d [Sat, 27 Aug 2016 13:57:20 +0000 (22:57 +0900)]
de0-cv latest merge
astoria-d [Sat, 27 Aug 2016 13:41:37 +0000 (22:41 +0900)]
testbench eliminated from de0-cv
astoria-d [Sat, 27 Aug 2016 13:19:30 +0000 (22:19 +0900)]
bg test ok, except for scrolling. sprite not displayed.
astoria-d [Sat, 27 Aug 2016 12:04:19 +0000 (21:04 +0900)]
ppu work update
astoria-d [Sat, 27 Aug 2016 11:59:13 +0000 (20:59 +0900)]
vram mem clock deferred.
astoria-d [Sat, 27 Aug 2016 11:39:49 +0000 (20:39 +0900)]
ale direction opposite...
astoria-d [Sat, 27 Aug 2016 11:23:31 +0000 (20:23 +0900)]
ale simplified.
astoria-d [Sat, 27 Aug 2016 11:22:57 +0000 (20:22 +0900)]
vaddr decoder bug fix.
astoria-d [Sat, 27 Aug 2016 11:01:25 +0000 (20:01 +0900)]
vram addressing method changed.
astoria-d [Sat, 27 Aug 2016 10:21:52 +0000 (19:21 +0900)]
vram access (attr tbl) timing complied to the nes specification.
astoria-d [Sat, 27 Aug 2016 09:06:12 +0000 (18:06 +0900)]
vram addr set timing changed
astoria-d [Sat, 27 Aug 2016 02:40:17 +0000 (11:40 +0900)]
script update
astoria-d [Sat, 27 Aug 2016 02:27:20 +0000 (11:27 +0900)]
latch clean up
astoria-d [Sat, 27 Aug 2016 02:22:03 +0000 (11:22 +0900)]
vram latch addr output timing changed
astoria-d [Sat, 27 Aug 2016 02:10:46 +0000 (11:10 +0900)]
bg enabled.
astoria-d [Sat, 27 Aug 2016 02:04:54 +0000 (11:04 +0900)]
gate sim ok. still working
astoria-d [Sat, 27 Aug 2016 01:57:55 +0000 (10:57 +0900)]
testbench update
astoria-d [Sat, 27 Aug 2016 01:47:10 +0000 (10:47 +0900)]
vram access changed
astoria-d [Sat, 27 Aug 2016 00:52:34 +0000 (09:52 +0900)]
sprite enabled, still working...
astoria-d [Sat, 27 Aug 2016 00:31:25 +0000 (09:31 +0900)]
plt ram access added
astoria-d@fc [Thu, 18 Aug 2016 11:56:48 +0000 (20:56 +0900)]
more render integration..
astoria-d@fc [Thu, 18 Aug 2016 11:33:53 +0000 (20:33 +0900)]
vga render inst integrated.
astoria-d@fc [Thu, 18 Aug 2016 07:53:47 +0000 (16:53 +0900)]
ppu reg code clean up
astoria-d@fc [Tue, 16 Aug 2016 11:07:14 +0000 (20:07 +0900)]
vram latch bug fixed...
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